IPGEN® - Publications

H. Bothe, U.Eichler, R. Jancke, K.-H. Rooch, M. Sylvester, R. Wittmann, "Integration of Design Optimization into Automatic IP Generation with 1Stone® and WiCkeD^TM", accepted for DASS2011, May 3-4 2011, Dresden
A. Graupner, R. Jancke, R. Wittmann,"Generator Based Approach for Analog Circuit and Layout Design and Optimization", Proceedings DATE2011, March 2011, Grenoble, France
Karl-Heinz Rooch, Roland Jancke, Reimund Wittmann, Harald Bothe, Matthias Sylvester, "Integration of Design Optimizaztion into Automatic IP Generation with 1Stone and WiCkeD", MunEDA User Group Meeting, MUGM 2010, Munich Germany
R. Wittmann, R. Jancke, H. Bothe and B. Oelkrug, "Rechnergestützter Entwurf wiederverwendbarer Analogschaltungen", Proceedings of GMM/ITG-Fachtagung Analog 2010 in Erfurt/Germany
F. Hummels, R. Wittmann and W. Schardein, "Specification based Generation and Optimization of a highly accurate Potentiometer for CMOS Processes", Proceedings of GMM/ITG-Fachtagung Analog 2010 in Erfurt/Germany
R. Wittmann, R. Kakerow, H. Bothe, W. Schardein, "A multi-purpose digital controlled potentiometer IP-core for nano-scale integration", IP 08 - IP Based Electronic System Conference, Proceedings, pp. 189 - 192, Grenoble, Dec. 2008
M. Kosakowski, R. Wittmann, W. Schardein, H.-J. Jentschel, "Yield prediction and optimization to gain accurate devices for analog design in nonideal nanoscale processes", 10th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM²ACD '08), Erfurt, Oct. 2008
M. Kosakowski, R. Wittmann, W. Schardein, "Yield optimization to gain reliable and area efficient data-converters using nonideal nanoscale processes", 2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf", Ingolstadt, Oct. 2008
M. Kosakowski, R. Wittmann, W. Schardein, "Statistical averaging based linearity optimization for resistor string DAC architectures in nanoscale processes", 21st Annual IEEE International SOC Conference, Proceedings, pp. 261 - 265, Newport Beach, Sept. 2008

J. Scheible, “Constraint-driven Design – Eine Wegskizze zum Designflow der nächsten Generation”, Analog 08 GMM/ITG Fachtagung “Entwicklung von Analogschaltungen mit CAE-Methoden” 02-04 April 2008, Siegen
R. Wittmann, D. Rosendahl, „Ausführbare Entwurfsablaufbeschreibungen für einen sicheren und effizienten Entwurfsablauf“, Silicon Saxony Workshop „Entwurf von integrierten Analog- / Mixed-Signal- / HF-Schaltungen“, 10. Mai 2007, Dresden
R. Wittmann, N. Nandra, J. Kunkel, M. Vanzi, J. Franca, H.-J. Wassener, Ch. Münker, “Life begins at 65 - Unless you are mixed-signal?”, Proceedings DATE 07, Nice, 16-20 April 2007, pp. 936-941, IEEE Computer Society, ISBN 978-3-9810801-2-4
R. Wittmann, R. Kakerow, Ch. Münker, W. Schneider, P. Pirrer, „DETAILS: Neue Möglichkeiten für die Konzipierung und den Entwurf von höchstintegrierten Endgeräten mit besonderer Berücksichtigung der eingebetteten HF-IP Baugruppen“, Newsletter Edacentrum 01/07, S. 5-13, April 2007
P. Birrer, S. J. Chandrasekaran, R. Wittmann, „Partieller Layout Flow zur Generierung von Auswahltabellen für Bussysteme“, Proceedings, 1. GMM/GI/ITG – Fachtagung „Zuverlässigkeit und Entwurf“, 27–28.März 2007, München
EDA Achievement Award 2006, German edacentrum, Edaforum 2006, Berlin Nov. 2006
R. Wittmann, J. Hartung, H.-J. Wassener, G. Tränkle, M. Schroter, “RF Design Technology for Highly Integrated Communication Systems”, Proceedings DATE 03, Munich, 3-7 March 2003, pp. 842-847, IEEE Computer Society, ISBN 0-7695-1870-2
R. Wittmann, D.Bierbaum, P. Ruhanen, W. Schardein, M.Darianian, “A unified IP Design Platform for extremly flexible High Performance RF and AMS Macros using Standard Design Tools”, System on Chip Design Languages (Extended Papers: Best of FDL’01 and HDLCon’01), ISBN 1-4020-7046-2, Kluwer Academic Publishers, Boston, June 2002
W. Schardein, R. Wittmann, “A design environment using C for effective layout synthesis and development of reusable libraries”, 1st IEEE International Conference on Circuits and Systems for Communication, ICCSC 2002, Proceedings, pp. 382–385, St. Petersburg, June 2002
R. Wittmann, W. Schardein, D.Bierbaum, M.Darianian, “SOC-driven design methodology for full custom high performance mixed-signal designs,” 13th Annual IEEE 2000 Int. ASIC/SOC Conference, Proceedings, Washington, pp. 148–152, Sept. 2000
D. Bierbaum, R. Wittmann, M. Buchmann, M. Darianian, “A 2k high speed CMOS embedded dual port SRAM using an advanced generator concept", Forschungsreport "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pp. 221–226, VDE Verlag, Feb. 2000
R. Wittmann, D. Bierbaum, W. Schardein, E. Matei, “A parameterizable and process retargetable high speed DAC for digital radio applications”, 12th Annual IEEE 1999 International ASIC/SOC Conference, Washington, Sept. 1999
R. Wittmann, W. Schardein, B. J. Hosticka, G. Burbach, J. Arndt, “Trimless high precision ratioed resistors in D/A- and A/D converters,” IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 935-939, Aug. 1995